the present invention relates to integrated circuit memory devices, and more particularly to arrangements of functional blocks in integrated circuit memory devices.
Integrated circuit devices such as integrated circuit memory devices are widely used in consumer and commercial applications. Integrated circuit memory devices continue to increase in integration density and speed, while allowing reduced power consumption. For example, synchronous Dynamic Random Access Memories (DRAMs) that can operate in synchronization with system clocks have been developed to allow high speed operation. Dual Data Rate (DDR) synchronous DRAMs also have been developed to allow high performance memory devices.
Electronic systems such as data processing systems often use buses including a plurality of signal lines to interconnect integrated circuit devices, so that the integrated circuit devices can communicate with one another. Output drivers are generally included in microprocessor logic and/or memory intergrated circuits in order to drive signals that are internally generated in the integrated circuit onto the bus. These output drivers are generally driven by voltage level signals.
Recently, however, in order to achieve high speed operations and/or other advantages integrated circuit devices that include current mode output drivers have been provided. The use of current mode output drivers can reduce the peak switching current and signal reflections on the bus, to thereby allow low power, high performance communications between integrated circuits.
One technology that uses current mode output drivers is the Rambus technology that is marketed by Rambus Inc., Mountain View, Calif. The Rambus technology is described in U.S. Pat. No. 5,473,575 to Farmwald et al., U.S. Pat. No. 5,578,940 to Dillon et al., U.S. Pat. No. 5,606,717 to Farmwald et al. and U.S. Pat. No. 5,663,661 to Dillon et al. Also see U.S. Pat. No. 6,072,747 to Yoon that is assigned to the assignee of the present invention. Integrated circuit devices that include current mode output drivers also will be referred to herein as Rambus devices.
Rambus devices may operate at high data rates, for example at data rates of up to 800 MHz or more. Moreover, large amounts of data may be simultaneously read from memory cell arrays in Rambus DRAMS, so that large amounts of power may be consumed.
The area of the integrated circuit substrate, the operating speed and/or the power consumption may be considered when designing a Rambus device. Since the area of the substrate, the operating speed and the power consumption may depend on the arrangement of the functional blocks thereof, the functional blocks should be arranged such that the area can be reduced or minimized, the operating speed can be increased or maximized, and/or the power consumption can be reduced or minimized. An arrangement of functional blocks in a Rambus Dynamic Random Access Memory (DRAM) is disclosed in U.S. application Ser. No. 09/280,026 to Yoo, filed Mar. 26, 1999, now U.S. Pat. No. 6,151,264, entitled Integrated Circuit Memory Devices Including a single Data Shift Block Between First and Second Memory Banks, assigned to the assignee of the present application, the disclosure of which is hereby incorporated herein by reference in its entirety. Another arrangement of functional blocks for a Rambus device is disclosed in U.S. application Ser. No. 09/466,536 to Moon, filed Dec. 17, 1999, now U.S. Pat. No. 6,256,218, entitled xe2x80x9cIntegrated Circuit Memory Devices Having Adjacent Input/Output Buffers and Shift Blocksxe2x80x9d, assigned to the assignee of the present application, the disclosure of which is hereby incorporated herein by reference in its entirety.
FIG. 1 is a block diagram showing the arrangement of functional blocks in a Rambus DRAM disclosed in the above-cited application Ser. No. 09/280,026. Referring to FIG. 1, the disclosed Rambus DRAM includes first and second memory banks 111 and 121, first and second core interfaces 113 and 123, first and second data shift blocks 131 and 141, all interface logic block 151, first and second input/output units 161 and 162, a delay locked loop circuit 163 and a pad block 171 in an integrated circuit substrate 101 such as a semiconductor substrate. In a Rambus DRAM of FIG. 1, the first data shift block 131, the interface logic block 151, an input/output block including, the first input/output unit 161, the delay locked loop circuit 163 and the second input/output unit 162 the pad block 171 and the second data shift block 141 are sequentially arranged between the first memory bank 111 and the second memory bank 121.
This Rambus DRAM may have a disadvantage in that the area of a substrate 101 may increase because the first data shift block 131 for the first memory bank 111 and the second data shift block 141 for the second memory bank 121 are separate blocks. Moreover, since the first and second data shift blocks 131 and 141 are remote from the delay locked loop circuit 163 which generates internal clock signals including an input control clock signal SCLK and an output control clock signal TCLK, the lengths of clock lines for transmitting the input control clock signal SCLK and the output control clock signal TCLK to the first and second data shift blocks 131 and 141 may increase. This may increase the load on the outputs of the delay locked loop circuit 163 and may increase power consumption.
Furthermore, since the first data shift block 131 is remote from the pad block 171, the length of a wire or conductor for supplying a power supply voltage from the pad block 171 to the first data shift block 131 may increase. This may cause noise to occur in the power supply voltage and/or a ground voltage which are supplied from the pad block 171 to the first data shift block 131, so that the operation of the Rambus DRAM may become unstable.
FIG. 2 is a block diagram showing an arrangement of functional blocks in another Rambus DRAM disclosed in the above-cited application Ser. No. 09/280,026.
Referring to FIG. 2, a Rambus DRAM comprises first and second memory banks 211 and 221, first and second core interfaces 213 and 223, an interface logic block 231, first and second input/output units 241 and 242, a delay locked loop circuit 243, a pad block 251 and a data shift block 261 in an integrated circuit substrate 201 such as a semiconductor substrate. In the Rambus DRAM, the interface logic block 231, an input/output block including the first input/output unit 241, the delay locked loop circuit 243, and the second input/output unit 242, the pad block 251 and the data shift block 261 are sequentially arranged between the first memory bank 211 and the second memory bank 221. Moreover, in this Rambus DRAM, a data shift block for the first memory bank 211 and a data shift block for the second memory bank 221 are integrated into the single data shift block 261. Consequently, the area of the substrate 201 of FIG. 2 may decrease compared with that in the Rambus DRAM of FIG. 1.
Furthermore, since there is one data shift block, the lengths of clock lines connected to an output of the delay locked loop circuit 243, for transmitting the input control clock signal SCLK and the output control clock signal TCLK, may be shorter than in the Rambus DRAM shown in FIG. 1. Accordingly, the load on the output of the delay locked loop circuit 243 may decrease so that power consumption may be reduced as compared with the Rambus DRAM shown in FIG. 1. In addition, since the data shift block 261 is adjacent to the pad block 251, a wire or conductor for transmitting the power supply voltage and the ground voltage from the pad block 251 to the data shift block 261 may be shorter. Consequently, noise occurring in the power supply voltage and the ground voltage may be reduced.
However, since the Rambus DRAM shown in FIG. 2 may be designed such that data lines L2 and L4 for transmitting data between the respective first and second input/output units 241 and 242 and the data shift block 261 are wired between pads in the pad block 251, the data lines L2 and L4 may be relatively long. Accordingly, loads on the data lines L2 and L4 may be relatively large, which may result in reduced data transmission speed and/or an increase in power consumption. When many pads and data lines are provided, the substrate area also may increase in a horizontal direction of the Rambus DRAM shown in FIG. 2 since the data lines are wired between the pads in the pad block 251. In addition, it may be difficult to accurately locate the pads in the pad block 251 in the middle of the integrated circuit in the Rambus DRAM shown in FIG. 2. Consequently, when Rambus DRAMS are incorporated into a module, the Rambus DRAMs may not be accurately packaged on a module board.
Integrated circuit memory devices such as Rambus DRAMs, according to embodiments of the present invention, include first and second memory core blocks in an integrated circuit substrate, each including a memory cell array and control circuits that control the memory cell array, a pad block in the integrated circuit substrate including a plurality of pads, and an input/output and internal clock signal generation block in the integrated circuit substrate comprising a data input/output unit that sends and receives data to and from external of the memory device via the pad block, a command input unit that receives a command input from external of the memory device via the pad block and a delay locked loop circuit that receives an external clock signal input from external of the memory device via the pad block and generates internal clock signals. A data shift block also is included in the integrated circuit substrate that sends and receives data to and from the data input/output unit and sends and receives data to and from the first and second memory core blocks in synchronization with the internal clock signals. An interface logic block also is included in the integrated circuit substrate that receives and analyzes the command output from the command input unit to control the first and second memory core blocks, the input/output and internal clock signal generation block and the data shift block. The interface logic block is located in the integrated circuit substrate between the first memory core block and the pad block, and the input/output and internal clock signal generation block and the data shift block are located in the integrated circuit substrate between the pad block and the second memory core block.
In other embodiments of the invention, the input/output and internal clock signal generation block is located in the integrated circuit substrate adjacent to the pad block and the data shift block is located in the integrated circuit substrate adjacent to the second memory core block. In other embodiments, a distance between the first memory core block and the pad block is equal to a distance between the pad block and the second memory core block. In other embodiments, the delay locked loop circuit is located in the integrated circuit substrate between the data input/output unit and the command input unit.
Accordingly, in integrated circuits Such as Rambus DRAMs according to embodiments of the present invention, the pad block need not be arranged between the input/output and internal clock signal generation block and the data shift block. Therefore, the lengths of wires such as data lines for transmitting data between the data input/output unit and the data shift block call be reduced. As a result, the loads on the data lines can be reduced, thereby allowing data transmission speed to be maintained and/or power consumption to be reduced. Moreover, the data lines need not be wired between the pads so that the width of the substrate need not be increased. In addition, the distance between the first memory core block and the pad block can be equal to the distance between the pad block and the second memory core block, so that integrated circuit memory devices according to embodiments of the present invention can be accurately packaged on a module board.